Day 4 @ TextielLab Textielmusuem Tilburg, NL
The palette is fixed and I’ve settled on my final design constraints and source material. For the next two working days in the lab, I’ll be weaving fragments from core memory dumps. Raw binary data from my system RAM have been rendered into a 6-bit color-space with a total of 64 colors. The data itself is a collection of fragments of files, images, sounds, temporary data and programs, a sketch of my activities assembled according to the obscure logic of my operating system.
Complete documentation of the process and resources will come in the following weeks.
After having my PC Laptop, camera, and audio recorder stolen on a train to Amsterdam, I am in debt to my dear friend Jeroen Holthuis for helping me write a program in Processing which performs variable bits per channel rendering of raw binary data in a similar fashion to Paul Kerchen’s LoomPreview. He has also been kind enough to loan me his camera and host me for some of my time in the Netherlands. Many thanks!
From May 1 through May 14th, Pete Edwards and Phillip Stearns have been working on developing an open platform for endless musical and electronic invention, exploration, and discovery from the bottom up or the top down. This system is based on minimizing the differences in the input and output “languages” used in various musical electronic formats. This means finding a way to allow free communication between logic, analog and eventually digital electronics. We are working to achieve this by finding a middle ground between these mediums where signal format and amplitude can be shared freely with minimal need for translators and adaptors. Our proof of concept models have shown that unhindered communication between binary logic and variable analog systems renders wildly adventurous possibilities and a unique musical character.
The form factor ethos is one where our passion for invention and performance are given equal attention. The key to achieving this goal is designing a hardware system with maximal scalability of size, quality and hardware format. Thus allowing the experimenter to quickly and cheaply connect circuit boards with simple jumper wires. Meanwhile the traveling musician may prefer to adapt their system to be held in a rugged housing with large format control hardware. This is effectively achieved by adopting a standard layout for a set of core modules which can be built up to the appropriate scale using a series of shields and pluggable add ons.
After a series of discussion on what such a system might look like and how to establish a standard that could be as flexible as possible, allowing for the nesting of micro and macro elements, we began prototyping modules and stackable hardware interfaces.
Project documentation is still underway, with schematics for the prototypes still in development, however, we have, after only two weeks, produced a functional system that fulfills many of our goals including portability, quick system (re)configuration, open patchable interconnection architecture, and stable breadboard compatible form factor with the potential for stackable shields and interfaces.
Future plans discussed for the project include the development of VCO, VCA, and VCF modules that operate on 5 volts, releasing schematics and system specifications to the public, production of low profile breadboard compatible modules in kit and pre-fabricated form with options for either through hole or smd components.
A video demonstrating the 4000 series CMOS logic based modules can be viewed here.
The Module Prototypes:
The Shifter – A dual 4-bit serial in parallel out (SIPO) shift register (CD4015) is connected as a single 8-bit SIPO shift register. Two 1 of 8 digitally addressable analog switches control two feedback taps which allow for each of the shift registers 8 outputs to be fedback to the register input. Input to the register is the output of four cascaded dual input XOR gates (CD4070) for a total of 5 possible inputs. The first two inputs are provided by the 1 of 8 switches, the third and fourth inputs are labeled as “mod” inputs for patching of any logic level signal, and the fifth input is connected to a “seed” button located on the lower left corner of the module. A logic level signal on the clock input will shift, or advance, the register once every positive going edge transition. Setting the feedback taps to the same state will fill the register with logic 0 each positive edge transition of the clock input. The register may need to be jump started by pressing the “seed” occasionally in the event that all outputs go low (lock up condition). The edge connector and header row provides connections for ground, power (3-18V), address and inhibit control inputs for each of the 1 of 8 switches, “mod” inputs, 8 parallel outputs of the register, and output from three of the XOR gates (1 = both feedback taps XORed, 2 = the second tap and “mod” inputs XORed, 3 = “mod” inputs XORed).
Divide by 2 by 2 by 2…- A single 12-bit binary counter (CD4040) takes a logic level signal and provides 12 sub-octaves, each available as patch points on the header on the left side of the module. Additionally, three 1 of 8 digitally addressable analog switches (CD4051) provide independent selection of the first 8 sub-octaves generated by the binary counter. The header row along the bottom provides connections for ground, power (3-18V DC), counter clock input, counter reset, address lines and inhibit control inputs for each of the three 1 of 8 switches, and the final four output stages of the binary counter.
Divide by 3-10 – This module divides a logic level signal frequency by integers 3 through 10. A 1 of 8 digitally addressable analog switch allows for the selection of the factor of division. A divide by 2 through 10 counter (CD4018) operates on feedback to establish the division factor and is used in conjunction with a quad 2-input AND gate (CD4081). The header row and connector provide connections for ground, power (3-18V DC), counter clock input, address lines and inhibit control inputs for the 1 of 8 switch, and the sub harmonic output.
Rhythm Brain – Three binary rate multipliers (CD4089) share a common clock input and output pulses that are multiples 0-15 of 1/16th the logic level signal on the clock input. All chips share a common “set to 15” input, which globally resets the pattern. Each chip has independent 4-bit addressable rate multiplication and inhibit controls. The edge connector and header row provide connections for ground, power (3-18V), 3 independent 4-bit address selection of rate multiplication and inhibit controls, and individual output for each chip. An additional set of outputs provide the compliment of the individual outputs on the header on the right side of the module.
3bit Digitizer – An incoming analog voltage is digitized and quantized in real-time at 3-bit resolution. Two quad opamps (TL074) are used as comparators connected to a resistor network which sets 8 thresholds at equal intervals from 0v to the Voltage supply level. An 8-bit priority encoder (CD4532) is used to convert the comparator outputs to 3-bits. The edge connector and header row provide connections for ground, power (3-18V), 3-bit output in order LSB to MSB, enable output, gate select output, and the 8 outputs of the comparators.